The present invention relates to the field of integrated circuits and their operation. More specifically, in one embodiment the invention provides an improved logic device, as well as an improved method of operating a logic device.
Logic devices and methods of their operation are well known to those of skill in the art. Programmable logic devices have found particularly wide application as a result of their combined low up-front cost and versatility to the user.
Altera's FLEX.RTM. and MAX.RTM. lines of programmable logic are among the most advanced and successful programmable logic devices. In the FLEX.RTM. 8000 logic devices, for example, a large matrix of logic elements (LEs) is utilized. In one commercial embodiment of such devices, each LE includes a 4-input look-up table for performance of combinational logic (e.g; AND, OR, NOT, XOR, NAND, NOR, and many others) and a register that provides sequential logic features.
The LEs are arranged in groups of, for example, eight to form larger logic array blocks (LABs). The LABs contain, among other things, a common interconnection structure. The various LABs are arranged in a two-dimensional array, with the various LABs connectable to each other and to pins of the device though continuous lines that run the entire length/width of the device. These lines are referred to as row interconnect (GH) and column interconnect (GV) or "global" interconnect lines. In Altera's line of products these may include what are referred to as "Horizontal Fast Tracks.TM.", and "Vertical Fast Tracks.TM.."
The MAX.RTM. 7000 logic devices by way of contrast utilize what are commonly referred to as "macrocells" (analogous to LEs) as a basic logic element. The macrocells are arranged in groups of, for example, sixteen to form larger logic array blocks (LABs). A programmable interconnect array (PIA) selectively links together the multiple LABs. The PIA is a global bus that is fed by all dedicated inputs, I/O pins, and the various macrocells. The PIA is analogous to global interconnect, GHs and GVs. For example, the PIA may be fed by signals that will be used as logic inputs, global controls for secondary register functions in the LABs, input paths from I/O pins to registers that are used for setup of the device, etc.
Inputs to the LABs include inputs from pins (via I/O control blocks), the PIA, and various control (e.g. clock) pins. Logic inputs are provided to one or more of five AND devices, the outputs of which are provided to a product term select matrix. The product term select matrix selects which inputs will be provided to an OR or XOR function, or as secondary inputs to registers in the macrocell. Product terms may be shared between macrocells for complex logic functions. Outputs from the LABs are provided to the I/O control block to the PIA and/or various output pins.
The FLEX.RTM. and MAX.RTM. logic devices have met with substantial success and are considered pioneering in the area of programmable logic. While pioneering in the industry, certain limitations still remain. For example, the present invention recognizes that it would be desirable to further increase the flexibility of such devices to perform logic.
From the above it is seen that an improved programmable logic device and method of operation therefore is desired.